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PRINICPAL SOFTWARE ENGINEER
THE ROLE:
Great opportunity for a Principal Software Development Engineer career professional to join an elite team to develop ongoing solutions in the Adaptive & Embedded Computing Group (AECG) division of AMD semiconductor. AMD’s new hardware programmable SoC FPGAs and Adaptive Compute Acceleration Platform (ACAP) deliver most dynamic processor technology and are achieving record performances in Data Center, Wireless/5G, Automotive/ADAS and Emulation applications.
These new applications, and heterogeneous computing architecture introduces new challenges in compilation, particularly in placement and routing. AMD’s Software Implementation Tools team addresses these challenges. This position within the Vivado Software group of AECG focuses on research and development of novel multi-threaded and multi-process algorithms and Machine Learning (ML) techniques.
THE PERSON:
AECG’s Vivado Software team is seeking a Principal Software Engineer with proven expertise in EDA Algorithms and C++ programming skills to work on a critical next generation state of the art Vivado Backend tool. The person will be part of FPGA Software Implementation Tools team within AECG having responsibility to innovate and develop novel Placer Algorithms and Machine learning techniques with aim of improving Quality of Results (QoR), Compile Time, and Memory Usage by orders of magnitude.
You will also be interacting with customers, helping them converge on their critical design requirements. This person will work with Tech Marketing and Applications Engineering to understand customer needs, and accordingly architect new features with ongoing engagement with Architecture team to design next gen FPGA and ACAP solutions.
KEY RESPONSIBILITIES:
- Innovate and develop novel Placer algorithms to get multi-fold performance improvements (QoR, Compile Time, Memory Usage)
- Interact with Customers, helping them converge on their critical design needs
- Collaborate with Tech Marketing and Applications Engineering to understand customer needs and accordingly architect new features
- Partner with Architecture team to design next gen FPGA and ACAP solutions
- Evaluating new FPGA architectures and its impact on existing EDA tools
PREFERRED EXPERIENCE:
- Proven expertise in EDA Algorithms
- Programming expertise with C++
- Machine Learning (ML) or Python
- Knowledge of Digital Design and Field Programmable Gate Array (FPGA) is a huge plus
ACADEMIC CREDENTIALS:
- Bachelor or Master’s Degree in Computer Science, Computer Engineering, Electrical Engineering, or related equivalent, PhD desired, but not required
Location:
#LI-JT1
Requisition Number: 185945
Country: United States State: California City: San Jose
Job Function: Design
Benefits offered are described here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
