The application window is expected to close on: 12/26/2024
Meet the Team
The Common Hardware Group (CHG) delivers silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
Your Impact
You will collaborate with architects, ASIC front-end and Design Verification teams to understand chip architecture, implement and get it verified. You will work closely with Back-end team on timing signoff for seamless physical design closure. You will also collaborate with the System and Software teams and participate in the journey from sample arrival through system validation to first customer shipments.
This role expects you to:
- Author micro-architecture specifications and participate in specification and test plan reviews.
- Architect and implement complex RTL designs.
- Scope third party IP requirements and solicit vendors.
- Analyze code coverage and provide feedback to the verification team to achieve coverage closure.
- Perform LINT and CDC checks.
- Triage, debug, and root cause simulation, software bring-up, and customer failures.
- Perform diagnostic and post silicon validation tests in the lab.
- Mentor and coach colleagues.
- Static Timing Analysis skills including generating constraints, performing quality checks such as setup, hold, transition and noise are considered advantageous.
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Science or related degree with 5+ years of ASIC design experience or Masters degree in Electrical Engineering, Computer Science or related degree with 3+ years of ASIC design experience
- Experience in Verilog/System Verilog programming skills.
- Experience in interactive and waveform debug skills.
- Experience with low-power design and clock domain crossings.
Preferred Qualifications
- Experience with scripting such as (Python, Perl, TCL, Shell programming)
- Networking knowledge preferred, but not essential.
- Have good communication, interpersonal skills and a keen interest to work closely in a team environment.
- Have a good understanding of the fundamentals of ASIC Design principles
#WeAreCisco
#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.
Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.
We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!
Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!
